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December 4, 2000 

This is Chapter 3 of the T X - 2 User's Handbook 
dated August , 1963. 

Help in obtaining the rest of this document, 
and other material on T X - 2 , including software, 
would be appreciated. 



Al Kossow (aek@spies.com) 



TX-2 USERS HANDBOOK 
CHAPTER 3 - OPERATION CODE 

TABLE OF CONTENTS 

Page 

3-1 BRIEF GUIDE TO THE ABBREVIATIONS 3-3 

3-2 OP CODE DESCRIPTIONS - (For In Out, See Chapter k. ) 3-5 

3-2.1 LOAD-STORE CLASS 3-5 

LDA, LDB, LDC, LDD, (LDE) - LOAD 3-6 

STA, STB, STC, STD, (STE) - STORE 3-8 

EXA - EXCHANGE . . . 3-10 

3-2.2 INDEX REGISTER CLASS 3-13 

RSX - Reset Index 3-l4 

DPX - Deposit Index 3-l6 

EXX - Exchange Index 3-18 

AUX - Augment Index 3-20 

ADX - Add Index 3-22 

SKX - Skip on Index 3-2^ 

JPX - Jump on Positive Index 3-26 

JNX - Jump on Negative Index 3-26 

3-2.3 JUMP-SKIP CLASS 3-29 

JMP - Jump (with variations) 3-30 

JPA - Jump on Positive Accumulator 3-32 

JNA - Jump on Negative Accumulator 3-32 

JOV - Jump on Overflow 3-32 

SKM - Skip on Bit 3-3^ 

SED - Skip if E Differs 3-36 

3-2.4 SCALE, NORMALIZE CYCLE 3-37 

SCA, SCB, SAB - Scale 3-38 

NOA, NAB - Normalize 3-40 

CYA, CYB, CAB - Cycle 3-l|2 



August 1963 



Page 

3-2.5 LOGIC, INSERT, COMPLEMENT/PERMUTE 3.45 

ITA, UNA, DSA, ITE - Logic 3.!^ 

INS - Insert 3.43 

COM - Complement/Permute 3-50 

3-2.6 CONFIGURATION MEMORY CLASS 3.53 

SEP, SPG - Specify 3. 54 

FLF, FLG - File 3.55 

3-2.7 ARITHMETIC CLASS 3.57 

ADD, SUB 3-58 

MUL 3.60 

DIV 3.62 

TLY 3.65 

3-3 OPERATION CODE CHART (Wesley A. Clark) 3-67 

3-3-1 NUMBER SYSTEMS 3-68 

3-3.2 GLOSSARY OF TERMS 3-68 

OPERATION CODE CHART 3-7I 

3-3-3 NOTES ON THE CODING CHART 3-73 

3-h CHAPTER 3 INDEX (Alphabetical and Numerical) 3-77 



August 1963 
3-2 



3-1 BRIEF GUIDE TO THE ABBREVIATIONS 



X J 


X Memory Register "J" 


[Xj] 


Contents of X Memory Register j 


T 


STUV memory address "T" (STUV memory is "£ 


T J 


T + [ Xj ] 


[*jl 


Contents of STUV Memory Register T 

J 


F a 


F memory register a 


[ F J 


Contents of F memory register a 


Q iv 


[T ] Configured as specified by a 


q. 


Quarter 


L 


Left Half 


R 


Right Half 


s 


Sign of 


SE 


Sign Extended (i.e. "With Sign Extension") 


==> 


Is copied into (Goes into) 



Examples : 






°[T] 


==> 


A 


Sq3(A) 


==> 


qhA 


[ *i ] 


==> 


L(T) 



The configured contents of STUV memory register T goes into the 
accumulator. 

The sign of quarter 3 of A is copied into all of quarter h of the 
accumulator . 

The contents of X memory register j goes into the left half of STUV 
register T. 
L [T] ==> X The left half of STUV register T goes into X register j. 
ql[T ] ==> F Q Quarter one of the contents of STUV memory T. is copied into F 
memory register a. 



The notation below is borrowed from the Hh Utility system. (See Chapter 6. ) 
(w) Register Containing w 

* Deferred address 

A,B,C,D,E The AE addresses: 377604, 377605, 377606, 377607, and 377610 

# The current location - i.e. the location of the instruction being performed. 



August 1963 3-3 



3-2 Op Code Descriptions 

3-2.1 LOAD, STORE, EXCHANGE 

LDA 
LDB 
LDC 
LDD 
LDE 

STA 
STB 

STC 
STD 
STE 

EXA 



August 1963 3-5 



LOAD AE (2l|-27) 
LOAD E REGISTER (20 ) 



IDA, 2k 


LDA 


LDB, 25 


2k 


LDC, 26 




LDD, 27 




LDE, 20 





a 



'LDA T, 



"[Tj] ==> A 



LOAD means copy into the AE from STUV memory. STUV memory is not changed. Activity, Sign 
Extension, and permutation are used. ALL load instructions except IDE perform the standard 
[T ] ==> E. 

EXAMPLES: **(Standard F memory - Chart 7-2) 



NO. 



INSTRUCTION 



CONFIGURATION 
DIAGRAM 



ABBREVIATED 
DESCRIPTION 



COMMENT 



: 



LDA T, 



111! 

W/// ///////////M 






==>A 
==> E 



.Since all four quarters 

are active, subword form 
20 



is immaterial 
30. 



LDA or 
IDA would be equivalent. 



LDA T, 



t t 



V//////M 



R[T, 



==> R(A) 
==> E 



The left half of A is 
not changed. 



11 



LDA T 



i 

[F u ] = 140 



II 



V///// /////////A 



sr[t, 



==> R(A) 
==> L(A) 
==>E 



The 18 bit word from 
STUV is "expanded" to 
36 bits through "sign 
extension." 



k. 



"LDA T. 
J 



-J t 1 

i mn 



L[T 



=*> R(A) 
==> E 



A "Right Half Load" - 
the left half of A is 
not affected. 



**A11 examples apply directly to LDA, LDB, LDC, and LDD. LDE is essentially the same - only 
the final M to E copy is omitted. 



3-6 



August 1963 



LDA, 2k 


LDA 


LDB, 25 


2k 


LDC, 26 




LDD, 27 




LDE, 20 





5- 


2 LDA A 




A 
(Before) 

A 
(After) 


L[A] ==> R(A) 
[A] ==> E 


The left half of A is 
unchanged. The right 
half becomes the same as 

the left. In a similar 

22 

manner, LDA A sets the 

left equal to the right. 

12 

LDA would clear the 

left half word through 

sign extension. 


1 1 

1 W////M 


6. 


l6 LDAT 

J 

[F lg ] = 163 




A 


lM*j] =* 0.1(A) 
Sql+tTj] ==> q2,3,4(A) 


The nine bit number in 
quarter k of T. is 
expanded to 36 bits in A. 


1 1 


1 ^< 1 


W///////////////A 


7- 


1 LDA {T k )* 




A 


R[(VjJ ==>R ( A ) 

[(T k ) j ]==>E 


This is double indexing. 

(it is not always faster 
because the defer cycle 
takes time also.) 


1 1 


11 


1 W////M 



August I963 



3-7 



STORE AE (34-37) 
STORE E (30) 



STA, 3k 


STA 


STB, 35 


34 


STC, 36 




STD, 37 




STE, 30 





a, 



'STA T 



J 



"[A] 



=> T, 



STORE is a non-destructive copy from AE to STUV memory. With a partially active configuration 
it 'becomes a partial store. Subword form is meaningless - only active pathways are used. The 
E register is set from the memory word after the store operation (except for STE which does not 
change E). 



EXAMPLES: **( Standard F Memory - Chart 7-2) 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
DESCRIPTION 


COMMENT 


1. 


STA T 





[A] ==>T. 
J 

** 


T is set from A, A is 

u 

not changed. Since all 

quarters are active, all 

are copied into T . 
J 


V////////////A T j 

t t f t 

1 1 A 




2. 


""■STA T 
J 




R[A] ==>R(T J ) 


Since there is no sign 
extension, STA would 
have the same affect. 
[F U I = 140 


1 Y/////A T j 

tl 

1 1 A 


3- 


2 STA T 

J 




H[A] ==> L(Tj) 

** 


12 

STA would he exactly 

the same. 
[F 12 ] = 142 


Y/////A 1 T j 

1 1 A 




k. 


2 STA A 




R[A] ==> L(A) 


This sets the left equal 

to the right (as does 

22 

LDA A). Since there is 

no sign extension on STA, 

12 

STA would do the same. 


Y/////A , 1 A 

1 1 A 



[F 22 ] 



232 



** After the store operation is complete, the new content of T . is copied into E except for 
the STE instruction which does not change E. 



3-8 



August 1963 



STA, 


3^ 


STA 


STB, 


35 


3^ 


STC, 


36 




STD, 


37 




STE, 


30 





5- 


5 STA T 

J 

[F 5 ] = 762 




A 


ql[A] 


==> a3(Tj) 


Quarter 1 is copied into 

quarter 3 of T.. The 

rest of T. is unchanged. 
J 


1 Y//A 1 


X 


1 1 




6. 


■""STE T 

J 

(Store E) 




E 


R[E] 


==> l(Tj) 


Stores in the right half 
only - useful for setting 
address sections - (For 
example, at start of sub- 
routines entered via hJPQ) . 


1 V////A 

\\ 

1 1 




7- 


STA {T k )* 




A 


[A] 


-*<Vj 


Double indexing - 


V/////////A 

tin 

1 1 





August 1963 



3-9 



EXCHANGE A (5*0 



EXA 
5U 



°EXA T. 
J 


°[A] ==> Tj 


a [Tj]==>A 



EXCHANGE A is a combination of STA and IDA. Sign extension, if any, occurs only in A and after 
the exchange of data. Subword form, Activity, and permutation are all used. 

The E register is set equal to the STUV memory word used. 



EXAMPLES: 



NO. 



INSTRUCTION 



CONFIGURATION 
DIAGRAM 



ABBREVIATED 
DESCRIPTION 



COMMENT 



1. 



EXA T. 



V// //AW M l i 

tttt 

Y//MWW/A a 



[Tj] ==> A 
[A] ==> T. 



EXA T 



i 



-W777A T j 



II. 



I W///X a 



H[Tj] ==>R(A) 
R[A] ==> S(Tj) 



i:l exa t 

J 

[F u ] = 11.0 



~W777A 



tl 



V//// /// ////A 



SR[T ] ==> L(A) 
R[Tj] ==>R(A) 
R[A] ==> R(Tj) 



Sign extension occurs in 
A, but not in T . 



"EXA T, 



V7Z77X 



^v 



Y////A a 



L[Tj] ==>R(A) 
R[A] ==>L(T J ) 



** The two copy operations that perform an exchange take place simultaneously. Remember also 
that E is changed - it is set equal to the final contents of the STUV memory word. 



3-10 



August 1963 



EXA 
54 



5- 


5 EXA T. 
[P 5 ] = 762 




A 


43[T ] — >qlA 
ql[A] ==> q3(Tj) 


## 


1 V/A 1 


1 V/A 


6. 


2 EXA A 




A 
(Before) 

A 
(After) 


R[A] ==> L(A) 


When "A" is used as the 
address section, EXA has 
the same affect as STA. 
No exchange is made, and 
there is no sign extension 


W////A 1 
1 X/////A 


7- 


EXA {T k J* 




A 


[A] ==> (Vj 


Double indexing: 
(T k )j = Tf^MXj]' 


Y////////////A 

till 

V///////////A 



August 1963 



3-11 



3-2.2 Index Register Class 

RSX 

DPX 

EXX 

AUX 

ADX ^ 

SKX REX, SEX 

JPX INX 

JIDC DEX 

SXD 
SXL 
SXG 
RXF 
RDX 
RFD 



** Supernumerary Mnemonics for SKX. 



August 1963 



RESET INDEX (RSX, ll) 



RSX 
11 



"rsx t 

J 


Q [T] ^ Xj 



RESET is a non-destructive copy from STUV memory into X memory. 

Subword form, Activity, and Permutation are used. 

The E register is set equal to the STUV memory word used . (Usually "T", but see example 7-) 



EXAMPLES: (Standard Configurations 


- Chart 7-2) 




NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
EXPLANATION 


COMMENT 


1. 


^SX T 

J 




T 


R[T] ==> X 

' [t] ==>e 


RSX vould do the same. 


I 1 1 1 1 


,11, 


mm 


2. 


2 RSX T 




T 
X J 


L[T] ==> Xj 
[T] ==> E 


T?SX would do the same. 
[F 12 ] = 142 


i i i i i 


^ 


Y//Y/A 


3- 


3 RSX T 

J 




T 
X J 


ql[T] ==>R(X J ) 

[t] ==>e 


The right half of X is 
set from T. The left nine 
bits are not changed. 


1 1 1 1 1 


1 


1 Y//A 


h. 


13 RSX T 

i 

[F 13 ] = 160 




T 
X J 


ql[T] ==>R(Xj) 
Sql(T) ==>L(Xj) 

[T] ==>e 


Sign of quarter 1 of T is 
extended throughout the 
left half of X . The right 
half is set as above. 33 RSX 
would do the same. [F ,] = 320 


1 1 1 1 1 


, 1, 


V////A 


5- 


21 

RSX. T 

fF 21 ] = 230 




T 

X. 




[t] ==> E 


Nothing happens (other than 
changing E) . 


1 1 1 1 1 


,11, 


1 1 1 





3-1^ 



August I963 



DEPOSIT INDEX (DPX, l6) 



DPX 
16 



"dpx t 


%1 => * 



DEPOSIT is a non-destructive copy from X memory into STUV memory. 

Activity and Permutation are used. 

The X memory word is expanded to a full 36 tit subword by extending bit 2-9 (the X register 

sign bit) but only active quarters are used. (The subword form is immaterial.) 

The E register is set equal to the STUV memory used . (Usually "T", but see examples 8 and 10.) 



EXAMPLES: (Standard F Memory - Chart 7-2) 






NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
EXPLANATION 


COMMENT 


1. 


"""DPX T 

J 




T 


jxj => R(T) 


Only the right half of T 
is changed. 


1 bV, -N| 


t t 


1 | 




2. 


2 DPX T 

J 




T 


[xJ =» L(T) 


Only the left half of T 
is changed. 




1 1 




3- 


DPX T 




T 
X J 


§: ] => R(T) 
SX => L(T) 


All of T is used. Note 
that DPX Q T (or DPX T) 
is a handy clear instruc- 
tion. ([*„] = +0 and can- 
not be changed. ) 


r\wv',-,i 
t t t t 


1 1 




k. 


3 DPX. T 





T 
X J 


R[xJ =» ql(T) 


Only quarter 1 of T is 
changed. 


1 KM 
t 


1 1 


5- 


DPX. T 
J 

[F l6 ] = 163 




T 
X J 


r[x_j] => q^(T) 


Only quarter 4 is changed 
for only one path is active. 


kr.M 1 




1 I 





3-16 



August 1963 



SP 



6. 


17 DPX T 
[F 1? ] = 202 




T 


SX -=*> R(T) 


All of T is affected. 


W//////W////M 


: ii 




7- 


21 DPX T 

J 

[F 21 ] = 230 




T 
X J 


SX =S>L(l) 


Surpri singly enough, this 
does do something. (See 
example 5, RSX.) 


W//////A 1 

ft 


■I II 




8. 


1dhc j <V* 




X J 




Deposit is indexable with 
deferred addressing. 


1 WlfflM 

tt 


1 1 




9- 


33 DKC T 

J 

[F 33 ] = 320 




T 
X J 


SXj — »-q3(T) 
[X^] =*ql(T) 


Note that bit 2-9 of X 

is used even though quarter 

2 is not active. 


1 V/M V//A 

t t 


! 1 1 




10. 


DPX 377720 




T 
X J 


[Xj] =>R(E) 

SX => l(e) 


V memory, except the A, B, 
C, D, and E registers can 
not be changed by any instruc- 
tion. Note that E is set to 
"what -would-have -gone -into- 
T. " 


1 1 


tilt 


1 1 1 





August 1963 



3-17 



EXCHANGE INDEX (EXX, lk) 



EXX 
Ik 



Q EXX T 

J 


Q [T] ==> Xj 



EXX is a combination of RSX and DFX- Except for sign extension, it does Just what its name 
implies - i.e. it will interchange words between X memory and SIUV memory. 



Subword Form, Activity, and Permutation are used. The E register is set equal to the STUV 
memory word used. 



EXAMPLES: (Standard 


F Memory - Chart 7-2.) 






NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
EXPLANATION 


CCMMENT 


1. 


hxx. T 


T 


R[T] ==>X 
[Xj] ==>R(T) 

[T] ==>e 




1 V///A 

tl 

l J L . 1 


Y////A *j 


2. 


2 EXX T 

J 


T 


L[T] ==>Xj 
[Xj] ==>L(T) 
[T] ==> E 




W///A 1 




V////A Xj 


3- 


EXX. T 
J 


T 


r[t] ==>X 
[X ] ==>R(T) 
S(X ) ==>L(T) 

[t] ==>e 


Note that left half of T 
is cleared. 


Y//////////////A 

tttt 


'>... W///A Xj 


k. 


3 EXX. T 
J 


T 


ql[T] «>R(X ) 
R[X ] ==> ql(T) 

[t] ==>e 


Nine bit exchange. 


1 V/A 

1 


1 WA 1 


5- 


EXX. T 


[F l6 ] = 163 


T 


Rtx^] ==>q!+(T) 
q ^[ T ] ==>R(X.) 
Sql^T) ==> L(Xj) 
[ T] ==> E 


Sign is extended in X 
but not in T. 


WA 1 


V//X//A x 

J 



3-l8 



August 1963 



EXX 

Ik 



6. 


17 EXX T 

J 

[F 17 ] = 202 


T 


[X ] ==>L(T) 
l[t] ==>Xj 
S(X ) ==>R(T) 
[t] ==> E 


Sign of X. is extended 
into the right half of T. 




1. 10^1 x 

J 


7- 


2L EXX T 

u 

[F 21 ] = 230 


m 


S(X ) ==>L(T) 
[T] ==> E 


Same as 21 DEX T. 


fc%%1 1 T 

ft 


i 1 1 X 


j 


8. 


Haocj {t/ 


T 


R[T k ] ==>Xj 
[X ] ==>R(T k ) 
[T k ] ==>E 


EXX is indexable if a 
deferred address is used. 


1 t%%t * 

tt 


Y/////A x 


9- 


33 EXX t 

J 

[F 33 ] = 320 


T 


Sq.l[T] ==> L(Xj) 

ql[T] ==> H(Xj) 

R[Xj] ==>4l(T) 

S(Xj) ==> q3(T) 

[T] ==> E 


Note that bit 2.9 is used 
for sign extension (not 1.9)- 


1 ^1 K^ 

, t. t, 
i V/W/A y 


J 


10. 


1 exx 377720 



T3S 


R[ 377720] ==>X 

[X ] ==>R(E) 
L[ 377720] ==> L(E) 


Same as """RSX. 377720. (Tog- 

J 
gle registers must be changed 

by hand. Note that E is set 

to what would have gone into 

T.) 


1 1 


mi 


V////A x. 



August 1963 



3-19 



AU3M3NT INDEX (AUX, 10) 



AUX 
10 



AUX T 

J 



[Xj] + °[T] ==> Xj 



AUX forms an 18 bit ring sum in X • There is no overflow detection. All of X. is affected. 
STUV memory is not affected. 

Activity and permutation are used. Sign extension applies to the operand taken from STUV mem- 
ory. If quarters 1 and 2 are active, subword form is immaterial. 

If one quarter of the STUV memory operand is inactive (as in standard configuration #3, for 
example), 40 is used for that quarter. 



The E register is set equal to the STUV memory word. (This is "T" except when a deferred 
address is used. See example 6.) 



EXAMPLES: (Standard 


F Memory - Chart 7-2.) 




NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
EXPLANATION 


COMMENT 


1. 


1 AUX T 

J 


T 


[Xj] + R[T] ==> Xj 
[t] ==> E 


Standard configurations 
#0, 11, 20, and 30 would 
do the same. 

[F u = ll»0 [F 20 ] = 200 
[v v ] = 600 


1 1 1 


1 1 


Y//////A Xj 


2. 


2 AUX T 

J 


T 


[x ] + l[t] ==>x. 
[t] ==>e 


Standard configuration 
#12 would do the same. 

[F 12 ] = 142 


II 1 


WWh Xj 


3- 


13 AUX T 
[F 13 ] = 160 


T 


[Xj] + ql[T] SE ==>X. 

[t] ==>e 


Standard configuration 
#33 would do the same (but 
NOT #3!) (See note n next 
page.) 
[F 33 ] - 320 


1 II 1 


t. 

V////A 


k. 


Q AUX. T 
J 

[Fj = 220 


f 


[Xj] + q2[T] SE ==>Xj 

[t] ==>e 


This has sign extension 
to the right. (There is 
no suitable standard con- 
figuration.) 


1 WA 1 


.1 , 

W/////A 

X J 



3-20 



August 1963 



AUX 
10 



5- 


21 

AUX T 

(J 


T 


[Xj] + (+o)==>x J 

[T] ==> E 


Register T is ignored, and 
X is not changed. Except 
for E, this instruction is 
innocuous. 


1 1 1 


II • 


1 V/////A t 


6. 


^•AUXj {T k l* 


T 


[X J ] + R[T k ]==>X J 


Same as example 1, but 
indexed via a deferred 
address. 


1 t%%t Tc 

. II 


W///A x 

J 



NOTE: E is cleared and then loaded as if by a LDE 



The sum of r[e] and [x ] then goes into X 



(circuitously) and E is set equal to the STUV register used (ie.[T] or [T ] if a deferred 
address was used). X. is always set. Note - If either quarter 1 or 2 is not part of 



an active subword, (as, for example, with standard configuration #3) one operand of the 
sum is not completely specified and +0 will be used as that part of the operand. 



August 1963 



3-21 



ADD INDEX (ADX, 15 ) 



ADX 
15 



ADX T 

J 



[Xj] + 



[T] ==> T 



ADX forms an 18 bit ring sum usually in STUV memory although only the active quarters are stored. 
There is no overflow detection. The operands are always 18 bit words - one from X memory the 
other from STUV memory. A configuration should be chosen such that the word from STUV memory 
has both quarters active, or is an extended 9 bit subword. If only one quarter is active, the 
inactive quarter of the operand is set to +0. 



Activity and Permutation are used. Only active quarters are stored, but sign extension applies 
to the operand taken from STUV memory. 

Die E register is set equal to the STUV memory word used. (This is "T" except when a defer is 
involved. See example 6.) 



EXAMPLES: (Standard F Memory - Chart 7-2) 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
EXPLANATION 


COMMENT 


1. 


"""ADX T 






T 


[x ] + r[t] ==>rt 
[t] ==>e 


Left half of T is not 
changed. The sum is 
standard 18 bit ring 
sum, also called "ones 
complement sum." 


1 V/////A 


tt 


1 1 




2. 


2 ADX. T 
J 




T 


[X ] + L[T] ==>LT 

[t] ==>e 


Right half of T is not 
changed. 


Y/////A 1 


1 1 




3- 


13 ADX. T 

[F 13 ] = 160 




T 

X. 




[X.] + qllTlgg ==> ql(T) 
[T] ==> E 


This gives a 9 bit ring 
sum. Configuration 33 
would do the same, #3 
would not. See note next 
page. The subword 
length should be 18 bits. 


1 V/A 

\ 

■ p 


1 1 





3-22 



August 1963 



ADX 
15 

NOTE: In example 3> the 9 bit result is an honest 9 bit ring sum only when X contains an 

extended 9 bit word. (See RSX, example h.) ADX cannot be used to add a 9 bit word to 
an 18 bit word. Use AUX. 



k. 



5- 



6. 



ADX T 
[P a ] = 220 



21 



ADX T 
[F 21 ] = 230 



1 ,* 



SSL 



w 



H x. 



I V// ///A x k 

ft 
C=l x. 



[X^] + q2[T] gE ==>q2(T) 
[t] «=>E 



[T] 



=> E 



[\] ==>e 



Essentially the same as 
example 3 except that 
the left half of X is 
significant. [F a ] illu- 
strated is 220. There 
is no suitable standard 
configuration. 



"Nothing" is done here 
because quarters 1 and 
2 are both inactive. 



Same as example 1, but 
indexed via deferred 
indexing. 



NOTE: E is cleared and then loaded as if by Q! LDE. The sum of R[e] and [X ] then goes into E 
a J 

and an STE is performed. Inactive quarters of the STUV memory word therefore remain 

unchanged. If either quarter 1 or 2 is not part of an active subword (as, for example, 

with standard configuration #3), one operand of the sun is not fully specified and +0 

is used to fill out the operand. 



August I963 



3-23 



SKIP ON INDEX (SKX, 12) 



SKX 
12 



SKX T 



SKX (or BEX, or SEX) provides 32 combinations of setting, adding, comparing, skipping, flag 
raising, and dismissing - all relating to X memory and without changing the AE or the E register. 
(See examples below. ) 

P memory is not used. The configuration syllable specifies the desired combination. (Examples 
1-8 show the use of bits k.6, 5, h and examples 10 - 12 illustrate bits k.8 and k-J.) 

"T", the address syllable, (or the final deferred address) is used as an OPERAND . 



EXAMPLES: 



NO. 


INSTRUCTION 


MNEMONIC 
ABBREVIATION 
(See Chart 7-3) 


ABBREVIATED 
DESCRIPTION 


COMMENT 


1. 


°SKX T 

U 


SKX T 

REX T 

J 

SEX T 
(Set) 


T==> Xj 


STUV memory is not used - 
"T" is the operand, not its 
location. The brackets []. 
were left out on purpose. 


2. 


■""SKX T 


(Set negative) 


-T ==> X 


"Minus" T - i.e. its ones 
complement is used to set 

V 


3- 


2 SKX T 

u 


INX T 

J 
(increase) 


[X j ] + T==>X J 


If the sum is zero, it will 
be -0 (all ones) unless [X.] 
was initially -K). 


h. 


3 SKX T 

J 


DEX.T 

J 
(Decrease) 


[X ] + (-T) ==>Xj 


"-T" is added to \X ]. Zero 
is -0. It cannot be -K). 


5- 


SKX. T 
J 


SXD T 
(Skip if X 
differs.) 


If [Xj] { T 
Skip - 
(i.e. #+2 ==> P) 


Skip if [X ] differs from T. 
Note: (+0) = (-0) and if 
[X ] is initially (+0), it 
is changed to (-0). 


6. 


5 SKX. T 



(Skip if X 
differs from 
negative. ) 


If fee ] J -T 
Skip - 
(i.e. #+2 ==>P) 


Skip if [X ] differs from 

-T. Note: (-0) = (+0) and 

if [X.] is initially (-0), 

J 
it is changed to +0. 


7- 


SKX. T 



SXL T 
(Skip if X 
is less.) 


If [X . ] < T 
Skip - 
(i.e. #+2 ==>P) 


Skip if [X ] is less than T 
and if [X ] -T does not over- 
flow. (Skip range: T-377777 
to T) Note: If [Xj]is ini- 
tially (+0), it is changed 
to (-0). 



3-24 



August 1963 



SKX 
12 



8. 


^SKX T 


SXG T 
(Skip if X 
is greater.) 


If [X ] > -T 
Skip 
i.e. #+2 ==>P 


Skip if [X ] is greater than 
-T and if [X ] + T does not 
overflow. (Skip range: -T to 
377777 -T) Note: If [X^J 
is initially (-0), it is 
changed to (+0). 


9- 


SKXj {T k }* 


REXj {T k }* 


T+ (\l "* X j 


[X,] is set equal to T.. e.g. 

a) SKX (0 k )* s set X 

from X . 

b) ''"SKX {0 )* = Comple- 

J V 

ment X.. 


10. 


10 SKX T 


RXF T 
(Reset and 
raise flag. ) 


T ==> X 
1 ==C> Flag 


For j = 1 to 37o, RXF ia the 



same as SKX for there are 

no flags for these numbers. 
Mote that flag zero can be 
raised. 


11. 


20 SKX T 

J 


RXD T 

J 
(Reset and 

Dismiss. ) 
(See note 3) 


T ==>X 

J 

DISMISS 


See Chapter h for the rami- 
fications of "DISMISS." 
If J = the current sequence 
number, "T" is nearly imma- 
terial for the subsequent 
change of sequence will 
change X.. 


12. 


3 °SKX T 

J 


RFD T 

(Reset, Raise 
flag, and Dis- 
miss.) 


T ==> X 

1 ==> Flag 
DISMISS 


This is used to change 

sequence number - often in 

the form - 3 °SKX #+1. It 

J 
is ignored if j = current 

sequence number. 



Motes: 1. "Skip" means "omit the next instruction. " i.e. "Go to #+2." 

2. The configuration syllable is united with the rest of the instruction. It may be 



■=! 1 ^ 
given redundantly, e.g. DEX is the same as J SKX or IHX or J DEX. 

The hold bit cancels DISMISS, (h SKX is the same' as SKX alone.) 

RXF cannot be used as a Jump. Index register "j" is indeed set, but it will not 

be copied into the P register, unless a change of sequence number occurs 

Chapter k.) 



(See 



August 1963 



3-25 



JUMP ON POSITIVE INDEX (JPX, 06) 
JUMP ON NEGATIVE INDEX (JNX, 07) 



JPX 06 

JNX 07 



JPX, T 



JPX and JNX are "Loop-closing", "Index-sensing" jump instructions. Their operation is as 
follows : 



[X ] is Sensed: 

(Zero is excluded. 
JPX jumps on POSITIVE. 
JNX Jumps on NEGATIVE. ) 



If it JUMPS: 

#1-1 ==> R(E) 

T ==> P 

DISMISS occurs unless 
cancelled via "h". 



1 


If it 


does 


i not: 


#n- 


==> 


P 


There is 


no DISMISS 


E is 


not 


changed. 



The increment is added: 



n + Xj ==> 



[X J ] 



(This is done whether 
it jumps or not.) 



Note: 1. If the sum is zero, it is -0. 

2. "n" is a signed integer: -17 to + 17g. 

3. F Memory is not used. 

1*. A deferred address determines where to jump to, but not if, and the second 
index register is not modified. 



EXAMPLES: 



Straight Table Scan (100 register 
table located at "TABL.") 



a.) JPX 

Start 



REX 77 



*•) 



Loop -* LDA TABL 

h" 1 JPX Loop 
J 

This program scans the table 
" backward through the manu- 
script." (i.e., highest 
memory location first. ) Note: 
X is initially set to + (n-l). 

J 



JNX 
Start 

Loop 



SKX 77 
LDA (TABL + 77) 
h +1 JNX Loop 



J 



This program scans "f orward 
through the manuscript." (i.e., 
lowest memory location first.) 
Note: X. is initially set to 
- (n-l). J 



3-26 



August 1963 



JPX 

06 



JNX 
07 



2. To scan every n table register 



a) START -* 



REX (TL - n) 
LDA TABL 

V 

h _n JPXj #-1 



b) START - 



•SffiX (TL - n) 
IDA TABL + TL - n 

J 

h** JNX, #-1 



These programs run for ( — ) iterations if ve assume that TL (Table Length) is an 
integer multiple of n. As written, they scan the first register of each block of 
n registers. To scan register "i" of each block, the LDA instruction could be 
written LDA (TABL + i) for example "a" (JPX) and LDA (TABL + i + TL - n) for 
example "b" (JNX). 

Interlaced Table Scan 

Scope flicker can be reduced by an interlaced table scan. The fact that the change 
in X is made after the jump decision causes a somewhat peculiar parameter configu- 
ration, but the program logic is essentially the same as above. For example, if "C" 
is the interlace, "TL" is the Table Length, and if "C" is not a factor of 



NOTE: 



program below scans the whole table with an interlace of C. 
TL, the program degenerates to example 2a.) 



'TL, " the 
(If "C" is a factor of 



START 



- ^REX C 
INX TL 

J 

LDA (TABL + C - l) a 
h~° JPX #-1 

J 

JMP#-3 



t" 












If C = 3, and TL = 7, the table is scanned in the following order: 6, 3, 0, h, 1, 
5, 2, 6, 3, 0, etc. 

1. "Zero" used as an address (as above) is always +0. 

2. M^ automatically puts a hold bit on JPX and JNX to cancel the automatic dismiss 
(see Chapter k and Chapter 6). 

3. The address of a deferred JNX or JPX is completely determined before the index 
register is changed. Therefore a 



JPX i S would jump to S = as defined by the 
a a a 



original contents of X - if it jumps at all. 



August 1963 



3-27 



3-2.3 JUMP SKIP CLASS 

JMP 
JPA 
JNA 
JOV 
SKM 
SED 



August 1963 3.29 



JUMP (With Variations) 



JMP 
05 



a 



'JMP T 



JMP is an unconditional transfer of control. It means go to T (or T.) for the next set of 

J 
instructions. The configuration syllable "a" does not refer to F memory but is used directly 

to provide 32 variations of JMP as illustrated below: 



DISMISS 

(See Chap, k) 

Saves last memory 
reference in L(E) 



in E(E)+ 



4.8 k 


7 k.6 k 


5 k.k 


1 1 1 








1 . 






Jit (#+1} ■*■ 









1 = "BRANCH" = An indexable JMP 
1 JMP = BRC = Go to T, 



1 = Saves return point (#+l) in X 

2 J 

JMP = JPS = Go to T, save 

return point in X . 



EXAMPLES: (See #10.) 



NO. 


INSTRUCTION 


SUPERNUMERARY 
MNEMONIC 


JUMPS 
TO 


COMMENT 


1. 


°JMP T 

J 


JMP T, 


T 


X. is ignored. 


2. 


"""JMP T 


BRC T 
(Branch) 


T J 


Indexable Jump = BRANCH 


3- 


2 JMP T 

J 


JPS T 
(Jump and Save) 


T 


Jump and save return point (#+l) in 
the specified index register (X,). 


k. 


3 JMP T 


BRS T 
(Branch and Save) 


T J 


Branch and save, X. is used to 

J 
evaluate the jump destination T 

J 
and is then reset to the return 

point (#+1). 


5- 


k 
JMP T 

J 


- 


T 


X is ignored, #+1 is saved in R(E) 

J 


6. 


5 JMP T. 
J 


1+ 
BRC T 


T J 


Return point (#+l) is saved in R(E) 


7- 


JMP T 


k 
JPS T 

J 


T 


Return point (#+l) is saved in R(E) 
and also in X,. 



t In MU terminology, the symbol "#" is an abbreviation for the location of the current 
instruction. (See Chapter 6.) 



3-30 



August 1963 



JMP 

05 



8. 


"^JMP T, 


^BRST 


T J 


X. is used to determine the jump 
destination T and is then reset to 

J 

the return point (#+l). The return 
point is saved in R(E) as well. 


9- 


10 JMP T 


- 


T 


The memory location of the last 
data reference is saved in L(E). 
(i.e. the contents of the Q 
register) 


10. 


1^ 
JMP T 


JPQ T 


T 


Jump, save "p" (i.e. #+l) and "q." 
(location of last data reference). 
This is the recommended jump, for 
the information saved is often of 
use in checkout. 


11. 


15 JMP T 

J 


BPQ T 


T J 


This instruction is the same as JPQ 
except that the Jump destination 
is indexed. 


12. 


l6 JMP T. 


JES T 


T 


Jump, save in E, and in X.. 


13- 


20 

JMP T 


JPD T 


T 


Jump, Dismiss. 


Ik. 


21 

JMP T 


BRDT 


T J 


Branch, Dismiss. 


15- 


22 

JMP T 


JDS T 


T 


Jump, Dismiss, Save in X.. 


16. 


23 JMP T 


BDS T 


T j 


Branch, Dismiss, Save in X.. 

u 



Jump and save return point (#+l) in the specified index register (X ). 

NOTE: A superscript numeral can be used redundantly on supernumerary mnemonics. For example: 
JMP = JES = JES = 2 JPQ = JPS etc. (Ml; "unites" them into the word.) 



August 1963 



3-31 



CONDITIONAL JUMPS 

JPA - Jump on Positive Accumulator 
JNA - Jump on Negative Accumulator 
JOV - Jump on Overflow 



JPA (1+6) 
JNA (hrj) 
JOV (1+5) 



a 



jpa a\ 



a 



JNA T, 



a 



JOV T, 



The conditional Jumps go to T. if the conditions are satisfied by any active subword . Permuta- 

J 
tion is ignored. The return point (#1-1) is saved in E if the Jump takes place. The accumulator 

and overflow flip-flops are not changed. Note that these conditional Jumps are indexable. 

EXAMPLES: 

#1. A Four-way Switch: 



JOV OF 
JNA Nl 
JPA PI 



** Goes to OF if overflow exists (Z. = l) 
** Goes to Nl if A is negative. 
** Goes to PI if A is positive. 
** Continues if A is zero. 



#2. Overflow: 

^ JOV T. is equivalent to ' JOV T,, for both configurations specify the same active 

J 

subwords. If any of the four overflow flip-flops are set to 1, control will go to 

T,. The overflow indicators (Z. ,Z ,Zp,Z ) are not cleared by JOV. 

Active subwords use the overflow indicator associated with the sign quarter, e.g. Z^ 
is associated with the right half word, Z. with the left half word. 

#3- To' Detect Minus Zero in an Index Register: 

(JNX. T or JPX T will not jump on either + or - zero.) 
J J 



DPX A 
■""DPX A 
JPA Tl 



** (0,,-0) or (0,,-HD) now in A 

** Goes to Tl if -0 in right half word. 

** Continues if +0 in both halves. 



3-32 



August 1963 



JPA (U6) 

jna hi) 

JOV (45) 



#1+. 18 Bit Zeros Again: 



20 JPA 


IP 


20 JNA 


IN 


JPA 


HI 


JNA 


HP 



** One half (or t>oth) positive - (Goes to IP) 

** One half (or hoth) negative - (Goes to IN) 
** Left (+0), Right (-0) - (Goes to PN) 
** Left (-0), Right (+0) - (Goes to NP) 
** Both (-K)) or Both (-0) - (Continue) 



August 1963 3-33 



SKIP ON BIT (SKM, 17) 



SKM 
17 



SKM . T 
q..b 



"Skip-on-a-bit" uses a one bit operand. It has 3 2 variations - some with Hk Supernumerary 
Mnemonics. The basic variations are as follows: 



^.9 ^.8 lf-7 h.6 k.$ k.k 
1 1 



00 - No skip « 

01 - Skip unconditionally 

10 - Skip if bit = 

11 - Skip if bit = 1 
("Skip" means "go to (#+2)" 
i.e. skip over the next 
instruction. ) 



u 



00 - No change 

01 - Bit is complemented 

10 - Bit is set to ("Make Zero") 

11 - Bit is set to 1 ("Make One") 



-•* If h.6 = 1, T is cycled right once. (Rotated) 



The bit in question is identified by its quarter number and bit number as diagrammed below: 



h-9. 



.k.l 3-9. 
I 



.3-1 2.9. 



2.1 1.9- 



1.1 



The meta bit is No. 10 (dec.)- (SKM is the only instruction that can affect it.) 

The parity bit is No. 11 (dec). I ^^ ^ ^ ^ changed ^ sm% 

The parity circuit is No. 12 (dec), j 

(Any quarter number will do for the parity and meta bits.) 



Bits and quarters are numbered from right to left and should be in subscript when used with SKM. 
(See chapter 6, page 6-7.) The bit designation goes in the "j bits" (3-6 - 3-1) > as follows: 



3.6 3.5 


3-* 


3-3 


3.2 


3-1 
















1 

rter No. ■* — 1 








-*. Bit 


Nui 



(00 refers to q» 



*- Bit Number (When given in the form indicated above, 
Bit Numbers are interpreted as Decimal, 
e.g. It-. 10 is the usual metabit designation.) 



SKM is therefore non-indexable except through deferred addressing. 

If a non-existent bit is selected, e.g. bit 0.0,1.0,2.0,3-0 for example, Unconditional Skips 
(SKU) and Rotate (CYR) will still work, but "makes" will do nothing, and conditional skips 
will not skip. 



3-3 1 * 



August 1963 



SKM 
17 



SUPERNUMERARY MNEMONICS (See Chart 7-3) 



MKC - SKM 
MKZ - 2 SKM 



MKN 



J SKM 



Make complement 
Make zero 
Make one 



SKU - X0 SKM - Skip unconditionally, (go to #+2) 

llr 



sue 



12„ 



SKM - Skip and complement 



SUZ - - SKM - Skip and make zero 
13c 



SUN 



SKM - Skip and make one 



SKZ - 20 SKM - Skip if tit =0 
21, 



SZC - 

SZZ - 22 SKM 



SZN 



23, 



SKM - Skip on zero and complement 

Skip on zero and make zero 
SKM - Skip on zero and make one 



SKN 



30, 
31 



SKM - Skip on one 



SNC - SKM - Skip on one and complement 

•52 
SNZ - SKM - Skip on one and make zero 

SNN 



33, 



'SKM - Skip on one and make one 



CTR _ SKM - Cycle memory once to the right (rotate) 
MCR - ^SKM - Make complement and rotate 
MZR - SKM - Make zero and rotate 



MNR - 


'SKM - 


Make one and rotate 


SNR - 


3 SKM 

2k 
SKM 

l!t SKM 


- Skip on one and rotate 


SZR - 


- Skip on zero and rotate 


SUR - 


- Skip and rotate 



NOTE: "Skip" is first, "make" next, and "rotate" last, 
and then rotate. 



k 26 

SZZ = SKM = Skip on zero, make zero, 



EXAMPLES: 

1. To copy a "bit: 



2. To clear n metabits starting at T 



SKZ 



**.: 



SUN T. 
MKZ T. 



1.1 
'l.l 



Sets tit T. 
equal to 
tit Qg 



1.1 



Rex a (n-1) 
^k.iolc? 

- 1 jpx a #-1 



** i.e. MKZ 



if.io^a 



{TJ* 



August 1963 



3-35 



SKIP IF E DIFFERS 



SED 
^3 



a. 



'SED T. 



Only P can 
be changed. 



SED compares all active quarters of E and T. according to the given permutation. If any 

J 
difference exists the next instruction is skipped over. No registers other than P (the central 

Program Counter) can be changed. (E is not changed.) Subword Form is immaterial. 
EXAMPLES: (Standard F Memory - Chart 7-2.) 



NO. 


INSTRUCTION 


DIAGRAM 


COMMENT 


1. 


SED T 

V 








E 


#+2 «► P if E differs from T 

J 

#+1 => P if they are identical 










MM 








2. 


2 SED T 

u 








E 


The left half of T is compared 
to the right half of E. ( 12 SED 
is identical.) [F 12 ] = ll»2. 




Xx 






3- 


22 

SED E 








E 
E 


The right and left halves of E 

17 2 
are compared. 'SED E, SED E, 

12 22 

SED E, or SED E would have an 

identical result. 




yy 







3-36 



August 1963 



3-2. k SCALE, NORMALIZE, CYCLE 

SCA 
SCB 
SAB 
NOA 
NAB 
CYA 
CYB 
CAB 



August I963 3-37 



SCALE 



0* 



SCA T, 



a [A]x2 a [ T jl==>A 



SCA, 70 
SCB, 71 
SAB, 72 



"SCALE" multiplies each active subword by "a power of 2," i.e. by 2 n where n is a signed integer 
specified in T . Each active subword can be scaled a different amount. The D register is used 
to count the binary shifts. The details are as follows: 

a) An LDD T is performed (with permutation and sign extension as called for). 

b) Each active subword (of A or AB) Is scaled according to its sign quarter in D , and 
these sign quarters are left set to -0. 

c) ''If an overflow exists for an active subword, the proper result is recovered by comple- 

menting the sign digit after the first shift, and the indicator is cleared. This rule 
is used for all operands - left (+), right ( ), and zero. Overflow can not affect SCB. 



Notice that SCALE amounts to shifting all the bits except the sign left or right and filling 
the vacant positions with copies of the sign bit (i.e. with +0). SCALE senses overflow and 
corrects the sign bit if necessary. SCA and SAB always clear the overflow flip-flop - even if 
bits are lost off the left end. SCALE never sets the overflow flip-flop. 



EXAMPLES: (SCB is illustrated to avoid overflow complications.) 



NO. INSTRUCTION 



CONFIGURATION 
DIAGRAM 



ABBREVIATED 
DESCRIPTION 



COMMENT 



1. SCB(-4,) 



llll 



] l-K) 



[B] x 2~ 4 ==>B 



q3,2,l[Tj] 



=> qMD) 
-> 4321(D) 



[-k, J is a M^ convention 
for A register with -U- 
in quarter k. See Chap- 
ter 6, page 6-7 and 6-10. 



2. 



30 SCB (N) 



N = 2775003000 



(8) 



lilt 



(N) 



ql^[B] x 2 ==> q^(B) 



,-2 



q3[B] x 2~* ==>q3(B) 
q2[B] x 2 3 ==>q2 (B) 
-0 ==>D 



Quarter 1 of B is not 
changed. The sign bits 
are never changed. Bits 
may be lost off either 
end without any alarm. 



3. 



SCB {If} 
N = 2775003000 



{»} 



(8) 



\n 



R[B] x 2 ==>R(B) 
-0 ==>q2(D) 
775 ==>ql(D) 



The left halves of B and 
D are not changed. 
Note that qh of (N) 
specifies the argument 
of the scale operation. 



3-38 



August 1963 



SCA, 70 

Note: Scale can of course be indexed - e.g. SCA T. where the argument comes from T . It is 

J J 

more common programming practice to use an RC word - e.g. SCA{-1,J. 

1*. Overflow: (SCA and SAB) 



a) To "recover an overflow": 



LDA {200 000 000 000} 
ADD (200 0Q0 000 000} 

SCA {-3,} 



b) Only active subwords are processed: 



**Acc. will now he 1*00 000 000 000 (a nega- 
tive number), and Z, (overflow bit #!*•) will 
be "1". 

**-3> s 7lh 000 000 000. After the scale, 
Ace. will be 0l*0 000 000 000 and Z. will be 
"0". Z_,Z 2 ,Z. are not sensed nor changed. 

(Any negative argument will suffice. ) 



LDA {200 300 toO 100} 
30 ADD (200 300 1*00 300} 



21, 



SCA (77 1 * Ilk 77 1 *- 77 1 *} 



L SCA {77^ 77^ 77^ 77*0 



**Acc. will be 1*00 600 001 1(00. 
**A11 four Z flip-flops will be "1". 
**0nly L(A) is scaled. Ace. will become 

01*0 060 001 1*00. Z^ will become "0", 

Z jZgjZ^^ will remain "1". 
**0nly R(A) is changed. Ace. becomes 

01*0 060 700 ll*0 and Z g becomes "0". Z, 

and Z x are still "1". 



Note that Z. ,Z_,Z_,Z 1 are overflow indicators . They tell whether overflow has 
occurred. An overflow resulting from negative numbers (as in q2 above) is not 
treated any differently. 



5- Subword forms for the AB register: 



a) "36" 

b) "18 - 18" 

c) "27-9" 

d) "9-9-9-9" 



L(A) 



L(B) 



<1^32 (A) 



S q>(A)! o>(B) S 03(A)! q3(B) 
1 , J I Li 



ql*32(B) 



R(A) 



R(B) 



S ql(A)j ql(B) 



S q2(A)[ q2(B) S ql(A)| ql(B) 

1 



Note that all of B is part of the subword. There is only one sign bit in anAB subword. 



August I963 



3-39 



NORMALIZE ACCUMULATOR 

NORMALIZE AB (Extended Accumulator) 



NOA 6k 
NAB 66 



"noa t. 




°[A] x2 nZ ==>A 
"[Tj] - nz ==>Sq(D) 



NORMALIZE scales just enough to remove leading zeros or to "recover" from OVERFLOW. It clears 
the active overflow indicators. The number of leading zeros (nz) is subtracted from the argu- 
ment from T. ( [T.]) and this difference is left in the Sign Quarter of D. If an overflow con- 
dition exists at the start, "nz" is -1, the scale is one place to the right, and the sign is 
complemented - just as for SCA or SAB. If nz is zero, it is +0. (See Note k- also.) 
\ 

NOA and NAB start with an LDD T . "nz" is subtracted from the sign quarter(s) and the rest 

u 



of D is not changed. The E register becomes a copy of T 
EXAMPLES: (Assume that NO OVERFLOW exists.) 



J" 



NO. INSTRUCTION 


DIAGRAM 


ABBREVIATED 
DESCRIPTION 


COMMENTS 


1. NOA(O) 




[A] x 2 nZ ==> A 

-nz ==> qMD) 
+0 ==> <i3,2,l(D) 


"nz" is the number of 
leading "zeros" in the 
original contents of A. 
("Zeros" can be positive 
zeros or negative zeros. ) 


(+0) 


.ii n. 


mmm» 




2. 2 N0A(0) 




R[A] x 2 nz ==> R(A) 

-nz ==> q2(D) 
+0 ==> ql(D) 


The left halves of A 
and D are not changed, 
"nz" is the number of 
"zero" in the original 
contents of the right 
half of A. Note that 
the result in D is a 
nine bit numeral. 


1+0} 


1 , , • 


1 Y////M* 


17 N0A[N) 

N = a,b,,c,d 

[F 1? ] = 202 




R[A] x 2 ZR ==> R(A) 

a-ZR ==> q2(D) 

b ==>ql(D) 

L[A] x 2 ZL ==>L(A) 

c-ZL ==> o>(D) 

d ==> cl3(D) 


"ZR" and "ZL" are the 
leading zeros of the 
right apd left 18 bit 
words of A. {N} is a 
register containing 
a,b,c, and d in quarters 
lt-,3,2, and 1. 


(N) 


■ >&. 


^^%^D 



tt BracketsO are used in the TX-2 Kk Assembly Program to indicate "Register Containing". 
See Chapter 6, page 6-10. 



3- to 



August I963 



NOA 6k- 
NAB 66 



°NOA{N) 

N = a,b,,c,d 
a = 400 



I I I I I fH) 



I \ U 



JD 



a>32[A] x 2 nZ ==> ql^32(A) 

a-nz ==> qh(j)) 

* ==> 13(D) 

c ==> q2(D) 

aJL[A] x 2 nz ==> 41(A) 

d-nz ==> ql(D) 



With a 27,9 split, 
t>oth counts will "be 
26 if [A] is zero. 
(See note on page 
3-61 .) 



A sample program -* Evaluate V «• xyz 

This product could have 105 significant hits (3 word lengths). One must resort to 
programmed arithmetic to get them all, hut normalize can he used to get the 3k most 
significant hits. Consider the programs below. 



Without Normalize: 



With Normalize: 



NOTE: 



LDA X 

MUL Y 
MOL Z 

This program puts the 35 left bits 
of the 105 bit product in A and 
essentially worthless numerals in 
B. The answer in A may be too small 
by 1 (in the 35th place). 



LDA X 

MUL Y 
NAB (0) 
STD T 
MUL Z 
SAB T 



With normalize, the product is given 

in AB, to 35+nz places from the sign. 

(it may low by 1 in the (35+nz)th 

place.) "nz", the number of zeros, 

is in T (in negative form), nz 

could be as much as 69 so the last 

SAB may not be desired. For example, 

if the NAB instruction above were 

replaced with NAB (34. ,) the answer 

in AB can be considered a 71 bit 

integer. 

NOA and NAB leave E set the same as the memory register used. 

If overflow exists, "nz" is -1 so [T ]+l ==> Sq(D). 

J 
NAB is essentially the same instruction - using the double length word (AB) instead. 
(See page 3-39 - "Subword forms for the AB register".) 

Normalize is an arithmetic instruction. The sign bit is not counted. "Leading 
zeros" will, of course, be plus or minus zeros - i.e., the same as the sign. 



August 1963 



3-M 



CYCLE 



CYA, 60 
CYB, 6l 
CAB, 62 



a, 



CYA T 



CYCLE logically falls in a class with LDA and STA, for it is most easily considered as a bit 
shifting instruction and the sign bit has no special significance. Bits shifted off one end 
are inserted at the other. None are lost. However, since the practical details of its use 
are so similar to SCALE, it is usually grouped with SCALE and NORMALIZE. The use of the 
memory word is the same as SCALE. 



b..\ An Q LDD T is the first step. 



b.) Each active subword is "cycled" or "rotated" according to its Sign Quarter in D 
and the sign quarter is left at -0. For cycle, the active subword has its ends 
connected - and can be considered as a ring of bits. If the number of places 
equals the subword length, the instruction does not change the subword. You can 
therefore arrive at any new position by cycling either way - the short way takes 
less computer time. The sign bit is handled no differently than the others and 
no bits are lost. 

c.) Overflow is ignored. 

d. ) The E register becomes a copy of the memory register used. 



EXAMPLES: Assume [A] = 123 U56 765 ^(Q) at the start 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
DESCRITPION 


COMMENT 


1. 


CYA(+1,} 




2^7 135 753 06k ==> A 

-0 ==> qlt(D) 

+0 ==> q3,2,l(D) 


One 36 bit ring cycled 
once to the left. 


1 1 |{+i,) 




2. 


3 °CYA{N) 
N=l,l,,l,l 




2U6 ==> q>(A) 
135 ==> q3(A) 
753 ==> 12(A) 
065 ==> ql(A) 


The four quarters 
are cycled separately 
i.e. four nine-bit 
rings, each one bit 
to the left. 


1 1 1 1 |{N} 

ilLL 



3-te 



August I963 



Assume [A] = 123 ^56 765 ^(q\ at the start. 



CYA, 60 
CYB, 6l 
CAB, 62 



3. 2 CYA(-3, } 




276 5^3 ==> R(A) 
-0 ==> R(D) 


The left halves of 
A and D are not 
changed. The right 
half of A (a ring 
of 18 bits) is cycled 
3 places to the right, 
i.e. one octal place.) 


1 1 1 t-3, ) 

L. ... ..J 


1 mm* 


DPX B 
h. CABC+3,} 

N=3,2,,5,-6 




23^ 567 65^ 320 ==> A 
000 000 000 001 ==> B 

-0 ==> q>(D) 
+2 ==> q3(D) 
+5 ==> 42(D) 
-6 ==> ql(D) 


The 72 bit ring -AB- 
is cycled 3 bits, 
i.e. one octal place 
to the left. 


1 1 |{H) 





ROTES: 1. The E register becomes a copy of the memory word used. 

2. CYA, CYB, CAB are indexable, and, of course, deferred addressing can also be used. 
(Neither of these is common. Most users use RC words.) 

3. CAB uses the same word structure as SAB and NAB. 



August 1963 



3-^3 



3-2.5 LOGIC, INSERT, CCMELEMENT/PEEMUTE 



ITA 
ITE 
UNA 
DSA 
INS 
COM 



August 1963 3-^5 



BIT LOGIC INSTRUCTIONS 



ITA 41 

UNA k2 

DSA 65 

ITE 1*0 



"iTA T, 



0£i 



[Tj] a [A] ==>A 



For these instructions, the word is considered as a string of independent bits - 
each bit column is a separate entity. For ITA, UNA, and DSA, the argument [T.], is all the 
active subvords - with sign extension if applicable. For these three, the E register is set, 
as usual, identical to the memory word used. 

For ITE, the operand is the active quarters only. There is no sign extension. The 
result, of course, goes into E and there is no final E register copy from memory. 

All these instructions are indexable and of course indirect addressing can be used. 



Name 


INTERSECT 


UNITE 


DISTINGUISH** 


Abbreviation 


ITA 

ITE 


UNA 


DSA** 


Symbol 


A 


V 


© 


Other Names 


"AND" 


Inclusive OR 


Exclusive OR 
Partial Add 


Logic 
Diagram 




1 




1 




1 


Q [A]° 
1 

Note th 
the "ca 
results 
additio 




1 

at this is 
rry" that 
from 
n. 


"[A] 

1 


1 

1 1 


a ° ° 1 
"[A] 

110 

Note that this is 
the Partial Sum. 



3-1*6 



August 1963 





(ITA) 


(UNA) 


(DSA) 


Epical 
Use 


Masking - e.g. 
if T contains 77 

ITA T; clears all 
of A except for the 
last 6 bits. 


Bit Setting, or 
clearing to minus 
zero - if T. contains 

77, UNA T, sets the 

last 6 hits to 1 with- 
out changing the rest. 


Bit Complementing - 
if T contains 77 

DSA T, complements 

the last 6 hits. 


Special 

Example 


30 SAB £-9, -9,, -9, -9) 
ITA B 


30 SAB (-9, -9,,. 9, -9) 
UNA B 


30 SAB{-9,-9,,-9-9) 
DSA B 


F 3 o= 6o ° 

All quarters are 
active and in- 
dependent . 


If "positive, A is 
cleared to +0. The 
original [A] goes in- 
to B. 


If Negative, A is set 
to -0. The original 
[A] goes into B. 


The absolute value or 
magnitude or each 
quarter goes into A 
The original [a] goes 
into B. 



** Note: DSA affects both the C and D registers. The effect on D is equivalent to LDD T . 
The effect on C is equivalent to forming the carries and uniting them with the original ^ 
contents of C. - i.e. ([A]a[T ]) v [c] ==> C. 



No- 



INSTRUCTION 



■Wt, 



CONFIGURATION 
DIAGRAM 



ii 



ABBREVIATED DESCRIPTION 



R [T ] v R [A] => R (A) 



COMMENT 



T is unaffected. 

The left half of A 
is also unchanged. 



11 



ITA T, 



LL 



R [T ] a R [A] => 

J 



E (A) 



SR [T^ a L [A] => L (A) 
[Tj] => E 



T is unaffected. 

Each bit of left half 
of A is "intersected" 
with bit 2.9 of T. - 
Hence, if R [T ] J is 
positive, L(A) J is 
cleared. 



"l 



:te t, 



R [T ] a R [A] => R (E) 



[f u ] = ito 



11 



T is unaffected. 

L(E) is unaffected. 
There is no sign 
extension on ITE. 



] T j 



R [Tj] © R [A] 



R (A) 



DSA T, 



II 



R [Tj] => R (D) 
[Tj] => E 
(R[T ] a A]) v R[C] => R(C) 



DSA affects registers 
A, C, D, and E. 
See note above. 



August 1963 



3-Vf 



INSERT 



INS 55 



a 



INS T, 



([A}A[B])v([B)A[ Tj ]) =>Tj 



Insert is a partial STA (store accumulator) instruction — only those bits marked by a 1 in 
the corresponding column of B are stored in T.. There is no sign extension, and [A] is not 
changed. If [B] is minus zero (all ones), INS is identical to STA. The E register is set 
to the final contents of the memory word used. 



EXAMPLES: (Standard F Memory - Chart 7-2) 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


MASK 
(CONTENTS OF B) 


COMMENTS** 


1. 


INS T 




-0 


[A} => T . INS is 

J 

identical to STA when 
[B] = -0. 


V////////A'h 
tttt 

1 1 A 


2. 


INS T 




0,, 777777 


R[A] =s»T.. This time 

it looks like a -""STA T , 

J 
because of the mask. 


tttt 

1 1 A 


3- 


3 INS T 

J 




M,,3A 


Bit 1.1 of A is copied 

into position 1.1 of T.. 

J 
Quarters 2,3, and h are 

inactive. No other bits 

1^ 
are changed. J INS T 

would do the same. 

[F 13 ] = 160 


VA^ 


t 

1 1 A 


h. 


INS T. 





M, ,3A 


Bit 1.1 of A is copied 

into position h.l of T.. 

Note that permutation 

has no effect on the use 

of B. INS T. is 


identical. 


YA T i 


""\ 


I I I A 



**In all cases, there is a final copy into E from the memory register used. 
t "Insert" is also given by ([A] v [b]) a ([b] v [t ] ). 



3-W 



August 1963 



HO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


MASK 
(CONTENTS OF B} 


INS 55 
COMMENTS** 


5- 


Suns (0^} j* 


i m 


A 


^,5,,6,7 


J STA • • • would be 
equivalent . 


, 


, 


i m 


6. 


INS T 




A 


+0 


Since [B] = +0, nothing 
happens . 


i 


tttt 

i i 




7- 


2 INS A 




(after) 

A 
(before) 


*,5„o,7 


4L[A]'->q3(A). Only 
quarter 3 of A is 
changed. (Because of 
the mask. ) 




i 





August I963 



3-^9 



COMPLEMENT - PERMUTE 



(PMT) COM 
56 



a COM T 

J 


°[ Tj ] => Tj 
T is permuted. 



COM - Complement - performs two basic operations. The active subwords of T are 
complemented (one's complement - all ones become zeros and vice versa) (with sign extension) 
and all quarters are permuted whether active or not. Note that if all quarters are inactive, 
COM permutes all quarters of T without changing the data. PMT is another abbreviation - 
equivalent to COM. 

There are k basic steps: 

1. [T.] => E , permuted according to a. 

2. Sign extension occurs in active subwords. 

3. Active subwords are complemented. ( [E] => Tl) 
k. [E] => T straight - no permutation. 

Note that, as usual, E is the same as T. at the end. 

EXAMPLES: (Standard F Memory - Chart 7-2) 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
DESCRIPTION 


COMMENTS 


1 


COM T 

J 




[ Tj ] => T, 
[Tj] => E 


All of T is 

complemented 


1 1 *1 


J w t . (before) 
V//////A *., 


(after) 


2 


2 C0M T 

J 






The halves are 
reversed and the 
right half is 
complemented. 


L[Tj] =>R(Tj) 
R[Tj] =>L(Tj) 


I I *j 


^•Ov.^ (before) 




V//A T i 


(after) 


3 


1 COM T 

t F i6] = 163 






Quarters 2, 3, 
and k are set to 
the complemented 
sign extension. 


q^[Tj] =>ql(Tj) 


I *J 


""->^^ (before) 

1 ^*~"-*w 1 


'////////A x h 


Sql^T J =>q2,3A(Tj) 


(after) 



3-50 



August 1963 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
DESCRIPTION 


COMMENTS 


k 


a COM T 

a = 172 

(all inactive) 






R[Tj] => L (Tj) 

L[Tj] => R (Tj) 
(Simultaneously) 


When all 
quarters are 
inactive, the 
data is not 
changed - it is 
merely pennuted 
according to 
the given con- 
figuration. 


1 1 






5 


COM CT k }* 




T 
T 




This has 
double index- 
ing. 

\i ' T + 

[\) + fXj] 


tV) 1=>T K,J 


1 1 


,1111, 
1 1 


t\,jJ => E 





Note: Since COM does not use any register other than T , there may he some confusion 

J 

as to the meaning of "Activity". In this chapter, quarters for which arrows are 
drawn are active. To be consistent with other instructions, one should say that 
the permutation comes first, complementing second, and sign extension last. If you 
use the phrase "Active Suhwords of T ", the order of the first two is immaterial 
since both operations can be considered to take place simultaneously. In any event, 
sign extension uses the complemented sign. 



August 1963 



3-51 



3-2.6 CONFIGURATION MEMORY CLASS 

SPF 
SPG 
FLF 
FLG 



August 1963 0.53 



SPECIFY FORM (SPF) 
SPECIFY GROUP (SPG) 



SPF (21) 
SPG (22) 



C SPF 


T J 


ai [Tj] 


=> F c 






q i [Tj] 


=> * c 






12 [Tj] 


=> F c + 1 


C SPG 


T J 


1 3 [Tj] 


=> F c-2 






1 h [Tj] 


=> F c + 3 



"Specify" copies from STUV memory into F Memory. (STUV memory is not changed. ) SPF 

s 

sets only one F Memory word. SPG sets four. F Memory addresses are consecutive modulo 3J fl - 
i.e., 0, 1, 2, . .., 36„, 37o>0, 1, 2, etc. These instructions are indexable hut not configur- 
able. The E register is set, as usual, to the contents of the memory register used. 

EXAMPLES: 



NO. 


INSTRUCTION 


DESCRIPTION 


COMMENT 


1 




SPF T. 




F is permanently set 

to +0 and can not he 
changed. 


2 


°SPG T 


°.2[Tj] -> F x 
1 3[Tj] => F 2 
qltlTj] => F 3 


Same as #1. 


3 


37 SPG T 


q. l[Tj] => F 3? 
q. 3[Tj ] => F x 
1 ^[Tj] => F 2 


F_ is, of course, not 

o * 

changed. The F 
Memory address "c" is 
normally given in OCTAL 



3-5^ 



August 1963 



FILE FORM 
FILE GROUP 



FLF 31 
FLG 32 



C FLF T 


[F c ] =>qi(Tj) 




[F c ] =>q.l(Tj) 




[F^l-xiadj) 


C FLG T 


[F^J^^Tj) 




[F c+3 ]=>qMTj) 



"File" copies from F Memory into STUV Memory. (F Memory is not changed.) File Form (FLF) 
copies a single 9 bit word, File Group copies four. They are indexable, hut not configurable. 
The F Memory Addressing is modulo 37„- i.e. "c" = 0, 1, 2, ... 360, 37g, 0, 1, 2, ... etc. The 
E register is set as usual, to the contents of the memory word used. 



EXAMPLES: 



NO. 


INSTRUCTION 


DESCRIPTION 


COMMENT 


1. 


°FLF T 


40 => qldj) 


F is permanently 
set to +0. 


2. 


°FLG T 

J 


=S> qlCTj) 
[F x ] -Xa^Tj) 
[F 2 ] ^^(Tj) 
[F 3 ] => ql^) 





3- 


3 FLG T 


[F 3 g] =S> ql(Tj) 

[F 3? ] => ^(Tj) 

■K) ->43(Tj) 

[F^ => ^(Tj) 


The F Memory address 
"c" is normally 
given in octal. 



August 1963 



3-55 



3-2.7 ARITHMETIC CLASS 

ADD 
SUB 
MUL 
DIV 
TLY (TALLY) 



August I963 



ADD (67) 
SUBTRACT (77) 



ADD (67) 
SUB (77) 



a ADD 


T J 


°[A] + a [Tj] => 


a A 


"SUB 


T J 


Q [A] 


- ^ -> 


°A 



ADD and SUBTRACT are straightforward one's complement (RINGED) arithmetic instructions. 
The use of configuration is similar to LDA. A zero result is negative except when both argu- 
ments are zero at the start -(+0) + (+0) = +0; K) -(-0) = +0. There are four overflow indica- 
tors--a separate indicator for each active subword. The indicator is cleared before the 
arithmetic is done and is set to a one for either type of overflow— (too negative or too positive). 
(With one's complement arithmetic there is a sign reversal when overflow occurs. The scale 
instructions take this into account.) Sign extension occurs prior to the arithmetic. The D 
register is set as if an \w T were done. The C register is set to the carries from 
each column, (in the case of subtract, "c" contains the carries from adding the complement 
of [T.].) The B register is unaffected. The E register is set, as usual, to the contents 
of the memoiy word used. 

EXAMPLES: (Standard F Memory - Chart 7-2) 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
DESCRIPTION 


COMMENTS 


1 


ADD T. 
J 




D 


[A] + [T ] => A 

[A] a [ Tj ] => C 

[Tj] => D 

[Tj] => E 


The expression 

[A] a [T ] => C is 

equivalent to saying the 
"carries" of each bit 
column go into the cor- 
responding bit column of 
C. Z. is set if over- 
flow occurs. 


1 1 


,1. 


III, 


W////////A 




2 


2 ADD T 

J 




D 


R[A] + L[T ] => R(A) 
R[A] a L[T ] => R(C) 
L[Tj ] => R(D) 
[Tj] => E 


The left half of the A, 
C, and D registers is 
unchanged. Z is set 

if overflow occurs. 


1 1 


r 1 


1 V////A 


3 


SUB T 




D 


[A] - [T.] => A 

[A] a [Tj] => C 

[Tj] => D 

[Tj] => E 


Z, is set if overflow 
occurs. 




,11 


-U, 


V////////A 



3-58 



August 1963 



ADD (67) 
SUB (77) 



NO. 



INSTRUCTION 



CONFIGURATION 
DIAGRAM 



ABBREVIATED 
DESCRIPTION 



COMMENTS 



k. 



3 LDA {277} 
3 ADD {307} 



M » 



606 
1 
207 
307 
307 



=> 41(A) 

=> z, 

=> 41(c) 

=> 41(D) 

=> E 



(277) is the Ml*- repre- 
sentation for "a register 
containing 277,g/'. 



5- 



°LDA (510,0} 
ADD (VfO,0) 




-m » 



201 
1 

too 

1*70 

470,0 



=> 41(A) 

=> Zj_ 

=> 41(c) 

=> 41(D) 

=> E 



(510,0} is the Mh rep- 
resentation for "A 
register containing 510/gx 

in quarter h, and zero 
in the rest of the word." 
See Chapter 6. 



Note: The four OVERFLOW indicators are associated with the subwords by Sign Quarter 
Number. See table below: 



SUBWORD 


OVERFLOW INDICATOR 


Quarter k 


h 


Quarter 3 


Z 3 


Quarter 2 


Z 2 


Quarter 1 


z l 


Left Half 


\ 


Right Half 


Z 2 


Full Word 


\ 


27 - 9 


Z. and Z x 



August 1963 



3-59 



MULTIPLY (76) 



MUL (76) 



MUL 



a [A] x a [ Tj ] => a (AB) 



"MUL" forms the double-length, ones- complement product of [A] and [T ] and stores it in 
A and B. The extra bit of B — at the extreme right -- is set equal to the sign bit of the 
product, i.e., to + 0. (Bit 1.1 of B = Bit k.9 of A after MUL.) 



H 



sign ^y 

Bit 



-Full Product 



_ +0 /Same as the\ 



Sign Bit / 

The use of configuration is similar to LDA and the relevant overflow indicator (correspon- 
ding to the active sign quarter) is cleared. No overflow can be generated. The active 
subwords of C are cleared to +0 and D is set as if an LDD T had been done. The E 

u 

register is, as usual, set to the contents of the memory word used. 



EXAMPLES: (Standard F Memory - Chart 7-2.) 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
DESCRIPTION 


COMMENTS 


1 


MUL T 

J 








[A] 


x [T ] => AB 

+ =>bit l-l(B) 
+ => Z^ 

+ => C 
[Tj'l => D 

[Tj] => E 


"AB" is the double 
length register 
diagrammed above. 
It is also used with 
SAB, CAB, and DIV. 
Bit 1-1 of B is 
set to + -- 
depending on the 
sign of the product. 






T 1 




1111 


D 




V////////A 


2 


3 LDA {5) 
%JL [h) 






D 


000 

050 

000 

00U 




=> q 1 (A) 
=> q 1 (B) 
=> q 1 (C) 
=> q 1 (D) 
=> h 


With standard con- 
figuration 3> 
ql[AB] is an 18-bit 
register composed of 
quarter 1 of A and 
quarter 1 of B. The 
other quarters are 
not changed 




1 

Y//A 



3-60 



August I963 



NO. 



INSTRUCTION 



CONFIGURATION 
DIAGRAM 



ABBREVIATED 
DESCRIPTION 



COMMENTS 



IDA (-3) 



MUL {-h) 



" " 
I 1 



+ ==> R(A) 

000030 ==> R(B) 

+ ^=> R(C) 

- h ==> R(D) 

- k ==> E 
==> Z„ 



The left half 
words are not 
changed. 



V.- 



IDA. { 3} 
MUL (-1*00) 



" t t ' t 



3 t j 



- ==> A 

- 3000 ==> B 

+ ==> C 

- 1*00 ==> D 

. too ==> E 

==> Z. 



£ LDA (3 ,, 0} 
2 MUL [k ,, 0) 




sm d 



+ ==> R(A) 

000030 ==> R(B) 

+ ==> R(C) 

+ k ==> R(D) 

(+Jf,,0) ==> E 
==> Z„ 



Only the right 
half words are 
changed. 



Note: When a 27-9 subword form is used, the Arithmetic Step Counter is set for the 
27-bit word, if it is active. This results in too many steps for the 9-bit 
word if it is active also. (This is true for MUL, DIV, NOA, NAB, and TLY.) 
Normal use of this subword form is for floating numbers of the form N = x • 2 y 
(27 hits for "x," 9 for "y"). Since different operations are performed on the 
two syllables, both subwords will not be active at the same time. 



August 1963 



3-61 



DIVIDE (75) DIV (75) 



°DIV T 


Q [AB] -f "[Tj] ==>A 


Remainder ==> B 



DIVIDE considers the contents of AB (except for the lowest order bit of B) as the 
numerator and the contents of T, as the denominator. (Note that it is compatible with MtTL. ) 
Configuration is similar to ADD, LDA, etc. The Quotient is stored in A with the appropriate 
algebraic sign. The remainder is stored in B with the same sign as the original numerator. 
(The sign of the remainder is at the left, as usual.) (SAB (+n) will bring strange bits into 
A for the remainder (in B) is not an extension of the quotient. ) 

[AB] SQ+ _R_ Q==> A 
[Tj] [Tj] R==> B 

The relevant overflow indicator is cleared at the outset and an overflow will be generated 
if | [A] I exceeds or equals | [T.] | . 

Note: 1. If | [A] | < 2 • |[T,]| overflow, if any, is guaranteed recoverable via 
SCA (-n) . SAB (-n) will also recover the correct answer, but it will 
destroy the remainder. 
2. If both [AB] and [T ] are normalized (as per NAB and NOA), the condition 

u 

above is met, and any overflow is recoverable. 
3- On overflow, the sign of A is always the reverse of the proper 

algebraic sign. 
k. If overflow is not recoverable, both [A] and [b] are useless. 

5. = N , and Overflow is set. (This is true for any N. ) 

+ 

6. = N , and Overflow is set. (Also true for any N.) 

- 

7. Divide clears C (as if by °1,DC (0) ) and sets D (as if by °I,DD T ). 

8. The contents of the memory register go into E, as usual. 

9. See also note on page 3-6l. 



3-62 August 1963 



EXAMPLES: (Standard F Memory - Chart 7-2.) 



DIV (75) 



NO. 



INSTRUCTION 



CONFIGURATION 
DIAGRAM 



ABBREVIATED 
DESCRIPTION 



COMMENTS 



1. 



DIV T 



J 



t t t t 



[AB] ♦ [Tj] 

Remainder 

+ 

[Tj 



=> A 

=> B 
=> C 



Overflow, if any, sets 



D 

E 



DIV T, 



JUL 



r[ab] + r[t ] 

Remainder 

+ 

R[T ] 



=> R(A) 

=> R(B) 

=> R(C) 

=> R(D) 

=> E 



Overflow sets Z„ 



The 



left half of the arith- 
metic unit is unchanged. 



J LDA (000} 
3 LDB (052) 
•W ( 5) 



00^ => ill (A) 

001 => q.l(B) 

000 => ql(C) 

005 => 0.1(D) 
005 => E 
=> Z, 



The numerator is actually 
half of 000052 since the 
lowest order hit of B is 
not part of it. In deci- 
mal, we have 21 * 5 or 
k with a remainder of +1. 



\ LDA ( -0 , ) 
LDB (725,) 
DIV ( -5,) 



+k => <il(A) 

-1 => ql(B) 

+ 
-5 

(-5,) ■ 



=> <ll(C) 
=> 41(D) 



=> 



E 



Note that [A] is minus 
zero. The numerator is 
therefore -21 (decimal). 
If [A] were +0, the 
numerator would be 

i^p(8) °r 23^ (decimal ). 



August I963 



3-63 



TALLY (74) 



TLY (74) 



°TLY T 


"[Tj] ==> A 

count of ones + [S D] ==> SqD 



TLY (TALLY) loads A (as does LDA). Then the count of ones is added to the sign quarter 
of D. The rest of D is not affected. The sign digit is counted also if it is a "one". 
The E register is set, as usual, to [T ]. 



EXAMPLES: 



NO. 


INSTRUCTION 


CONFIGURATION 
DIAGRAM 


ABBREVIATED 
DESCRIPTION 


COMMENTS 


1. 


TLY T 


1 1 '', 


[Tj] =>A 

n+ql4-[D] => qto 

[Tj] =>E 


"n" is the numher of 
ones in [T. ]. The 

addition is regular 9-t>it 
ring addition with no 
overflow detection. 


Jill, 

Y/////////A a 


2. 


TLY (+0) 




+ => A 
+ => E 


The D register is not 
changed 


1 1 (-K)] 

,IHI, 

W/////M/A a 


3- 


"'"TLY (-0) 




- => R(A) 
l8+q2[D] => q2D 

- => E 


The left half of A is 
not changed. Only the 
sign quarter (No. 2) of 
D is affected. 


1 1 C-o) 

11 


1 V/////A A 



Note: When a 27-9 subword form is used, the Arithmetic Step Counter is set for the 
27-bit word, if it is active. This results in too many steps for the 9-bit 
word if it is active also. (This is true for MUL, DIV, NOA, NAB, and TLY. ) 
Normal use of this subword form is for floating numbers of the form N = x • 2^' 
(27 bits for "x," 9 for "y"). Since different operations are performed on the 
two syllables, both subwords will not be active at the same time. 



August I963 



3-65 



3-3 OPERATION CODE CHART (Wesley A. Clark). 



August 1963 3-67 



3-3-1 Number Systems 



Let S be a binary number of length X 
3 number ranges are commonly used: 

1) Positive Integers (e.g., r, P, Q) 
< S < 2 A - 1 

2) Signed Integers (e.g., X ) 

- (2 V1 - 1) < S < + ( 2 V1 - 1) 

3) Signed Fractions (e.g., A in MUL, DIV ) 

- (1 - 2' (V1) ) < S < + (1 - 2 _(V1) ) 

Negative number represented "by " Ones Complement " of corresponding positive 
number. S Q 1 S (complement of S). 

Two representations of number zero = 00 ... l 

= 11 1 I length 

Reduction Modulo £ 

For positive integer S < S < 2 u 



S modu 



S if S < u 
S - u if S > u 
Example: 6 mod J = 6, & mod 7=1 



3-3.2 Glossary of Terms 

h Hold bit 

c Configuration 

i Instruction 

J Index 

r effective address 

W memory operand 

W * Permuted Memory Operand 

W . Memory operand (indexed) 

W * Permuted Indexed Memory Operand 

r,r®X. Operand addresses 
J 



D' Leftmost (sign) quarter of D 
(W .*)' Leftmost (sign) quarter of permuted indexed memory operand 
G Group c 



3-68 August 1963 









EXAMPLF 


1 


EXAMPLE 2 


S, T 


X-bit binary numbers 


S 


010 Oil 


101 


111 


Oil 010 


S 


Complement of S (sign bit complemented] 


S 


101 100 


010 


000 


100 101 


< s > 


Inversion of S 


< S > 


110 Oil 


101 


OH 


Oil 010 


RS 


Positive (counterclockwise; left) unit 
rotation of S 


RS 


100 111 


010 


110 


110 101 


*'h 


Negative (clockwise; right) unit 
rotation of S 


R- X S 


101 001 


110 


Oil 


101 101 


2 x S 


Unit positive scaling of S (S scaled 
up by one) 


2 x S 


000 111 


010 


110 


110 101 


2 -1 x S 


Unit negative scaling of S (S scaled 
down by one) 
(scaling is rotation without change 
of sign bit) 


2" 1 x S 


001 001 


110 


111 


101 101 


n(S) 


Normalizer of S (S signed fraction) 

| < | 2 n(S) * S | < 1 

Note: n(0) = n(o) = X -1. (Used as 
9-bit number. ) 


n(S) 





2 


t(S) 


Tally of S (number of ones in S) (used 
as 9-bit number. ) 


t(S) 


5 


6 


T 


Oil 010 


Oil 


Oil 


010 Oil 


S * T 

S v T 
S® T 


S and T 

S or T 

S or T but not both 


for each bit 
b, b=l, 2, 
... f A 


S A T 


010 010 


001 


Oil 


010 010 


S v T 


Oil Oil 


111 


111 


Oil Oil 


S© T 


001 001 


110 


100 


001 001 


sei 
s e t 


A-bit binary ring sum 
Nnt.fi:, R » S m 

A-bit binary ring diff 


of S and T 


© 

S 0T 


101 110 
111 001 


000 
001 


010 
100 


101 110 
000 111 


erence = (S © T) 



Enclosed expression applies to each active quarter of Operand 



Enclosed expression applies to each active subword of operand 



A blank box indicates that no change is made. 



August 1963 



3-69 



INSTRUCTION EXECUTION TABIC. IwTnutriw.fh.e., 1 ,/,a| durtm ««»,.».».«« m rr»« « '»;Pfc v»uit<) 


fMCHMM 


' 


wo 


nam 


HiilitilW 


p « 





X, 






2W 


A 


B 


c 


D 

D' D 


E 


O 


Zl 


»rr 


«VfClFV rtMHM 






























® 


» 


«K 


sncirr Mow^Z 




P*l 


A*Xy 
























1.2. 


jr 


rir 


pili roAn 










Pv® 
















2.8 


H 


rt* 


rat frnoup 










Gv 



















M 


LM 


IOA0 A 




P*» 


AfcXj 














w«- 








® 


» 


(Do 


VOAO ■ 


















V# ' 








2i 


IDC 


IOAB e 




















wi < 






n 


100 


LOAD D 
























w.7 1 


l.l 


» 


STA 


ITOKt A 












A 














if 


4T» 


JTOAC 












• ' 














u 


JTC 


JTOM e 














C 














>r 


STO 


STOftf 












D ' 














M 


«»A 


E*bMM*4C A 


a 










. A S 




<, 








2.+ 


« 


m» 


INSCAT 












<».A> «■ 
.(IaVC) 

















♦1 


IT* 


MTIMICT A 
















A«W5 "■ 










41 


VM 


umitc A 
















A.WJ 








<f 


MA 


MtTWOVISH A 
















A»*tt ' . 


[A» Wil.C ^ 






«t 


AM 


AW 














© 


A»w{ ' 


A.wi < 


1 


77 


J« 


suoriiMr 














A«W5 ' 


A»at " 




If 


1/ 


815 


7» 


•W 


Mwnrtr © 














o' 


A « W.J 


» 




« 


a 


37{* 


J» 


M* 


•*»••* © 


® 












(3 


f*»A<ju.; (*/kv«..' 






(0 


OTA 


CWU A 
















r^O-A ' 


■ ' 




- ' " '■•, 


— i 
® 


*» 


CA> 


evtit At 
















*^^. 




(1 


CT» 


CVCIC ■ 


















V^'fi ' 




y 3 

JX1*0 


TO 


JCA 


>CAlt A 


XCAIaO 












« 


^:a ' 






Uff>t 












l««W 






IH>I * 












t&.Vuf 




71 


MB 


KAIC At 


«•>..' 












W-At 




*H*»i ^ 












d — ■ — i 


_ 


Ka|>i ^ 

*ai'«» 












aW«.<«-'.At> ' 


, _ 


71 


*• 


JCAII | 


















J^.B " 




% 


4« 


MOA 


WOHNAUlt A 


««•• 












« 


«w ■■ — 




(WJ)'b«(a) " 


«+.' 












<r"-A> 






(w5)'«i ' 


<> 


KA* 


MAWMLISt A* 

© 


»«•• 












«-«-'.Ai 




«)'e«fru' 


iW-l' 












<«-'-AB> 




(WO'n 


HE 


6|2 


T» 


nr 


TAll» ® 
















Kf " 






o'**fr^)' 




3.6 


12 


Sic* 

M 


JKI» ow 
CNOI* 


c<» 


/>♦' 







A 






















© 


1 


-A 


2 


Xj®^ 




p*t 


3 


*I©A 


»-7 





2.0 


« 


PWT 


ri»n«Ti 


«»«IT 


p«i 


A*Xy 








WS 
















® 


con 


C*M*tfnrNY 


© 






«>1 


t«r 
















o 


20 


lot 


WAO ( 


























v« " 


1.2 


M 


srr 


srom 1 












c ' 
















o 


W 


IT! 


ixrimitT I 


























uwr, A 


«J 


»1D 


i«i» ir 
t oirnAt 


ti'wj' 


























t«W3 


P»2 
























2.0 


17 


»t» 


l*l»-HAItr 


a 


» 


A. 




© 




















® 


- 






- 






















- 


- 


- 


- 




o 


II 


MX 


M»tT It 




P» 1 


A 


fttfl ' 






















® 


1.2 


rt 


DM 


MMIIT X 








WKyW*" 


















1.2 


1* 


exx 


CftCHAWftf X 




(ktf) ■ 




S.WX/' 


















.8 


le 


AUK 


ai>»mkwt x 




«y»(K')fc 




© tf? 


















3.2 


15 


A»X 


A»» X 








^•(W* 


















- 






- 


- ■ 


- 


- 






. 








- 


- 


. 


. 


. 


- 


3.2 


04 


JTX 


jvnr •* 
M«iTi«r X 


*v«# 


P*l 




£©X,' 






















- 


x>->« 


A 


























07 


JNX 


JVMf OM 

w*«nv« X 


*l<0 


X/»0 


P» i 


























i.G 


«* 


jm 


nitir e* 
►•tiTiyf ^ 


A»» 


P»l 




























A >0 


A«X; 


























' r*i 


♦7 


TKA 


J*.* •* 


A«0 


*A*0 


P 


























1 


« 


jov 


•vfRfftaw 


Z(AVI 


























1" 


USel 


A»X f 


























*r.i 


1.2 


OS 


JMf 


JUHF 


«. •*•* 


A. 




© 






















©: © 


• AC 


■IIAXCH 


e «*4 


A*X/ 




tr 


T»D 


TltA««riR 
»ATA 


*■*•* 


P 


































•"^ 


r ♦! 


AMj 








@ 


@ 














® 



August 1963 



3-71 



3-3-3 Notes on the coding chart 

1. In all expressions P + 1, P + 2, sums are reduced modulo 2 
(777777 + 1) mod 2 18 = 0. 



18 



2. For SPF and FLF only quarter one of W is used. SPG and FLG use all 
four quarters. F memory addressing is counted modulo 37g (e.g., 36, 37, 
0, 1 ...) 

3. If r 9 X = 3776o4 (address of A reg. ) then EXA has same effect as STA . 



k. 
5. 



Final value of W fi ==> (Q = r, r 9 X ). 

ADD , SUB overflow conditions: 

If A © W = A + W Then ==> Z(A) 

If A9W/A + W Then 1 =*> Z(A) 

Z(A^) = ZfA^) h z(A kl ) * Z(A k ) = Z L 



■\L' 



Z(A 3 ) 



Z(A2 X ) ■ Z(A 2 ) = Z 2 
Z(A L ) = Z x 



DIV Conditions: 



CONDITIONS 


Z(A) 


A 


B 


|w rJ *l ^ 


|W r1 *|> |AB| 





1 
QUOT 


REM 


|W rJ *b |AB| 


1 ^ 


JUNK "^ 


JUNK ^ 


|w rJ *| =0 


|AB| = 


1 


A 




|AB| ^ 


A ©W * 


R^B 



Sign of normal remainder = sign of dividend (AB). 
JUNK is recoverable if |A| < 2 |W r *| . 

7. Exceptions in MUL , DIV , NOA, NAB, TLY : 

Expressions listed are not correct for quarter (subword) 1 of A, B, and D' 
if a 27, 9 subword is chosen, and if quarter 1 is active. 

8. CYCLE, SCALE , and NORMALIZE instructions begin, in effect, with LDD. 



FMT, COM consist of 3 consecutive steps: 



w * = 


=> E 


1 


t 


W * = 


=> E 




♦ 


E ==> 


w * 





August 1963 



3-73 



10. SKM variations: 



3 


M r a b '' selected bit 
M r.q.l0(dec) = m r 

r.q.ll(dec) = p r 
M r.q.l2(dec) s * ar11 * ( M r ) 


q mod k 


b 


3.6 


3-5 


3-* 


3-3 


3-2 


3.1 


q = quarter; b = bit 



FUNCTION 


CONDITIONS 


r.q.b 


ACTIONS 
(SKIP, Then MAKE, 
Then CYCLE) 


c 


I4..8 U.7 h.6 k.5 k.K 




0. - 


- 


P + 1 ==> P 


SKIP 


1 - - - 


- 


P + 2 ==> P 


SKIP on 
ZERO 


1 - - - 





P + 2 ==> P 


1 


P + 1 ==> P 


SKIP on 
ONE 


1 1 - - - 





P + 1 ==> P 


1 


P + 2 ==> P 


- 


- 


- 


_ 


COMPLEMENT 


- 1 


- 


M . ==> M ' 
r.q.b r.q.b 


MAKE ZERO 


- - - 1 


- 


==> M . 
r.q.b 


MAKE ONE 


- - 1 1 


- 


1 ==> M . 
r.q.b 


- 





- 


_ 


CYCLE 


1 


- 


r" 1 w ==> w 

r r 



11. S„(X.) is 18-bit number 00 

G J 
is or 1. 

12. ADX , AUX consist 
of sequence of steps : 



or 11 ... 1 according as sign bit of X, 





==>E 








T 






W r * ==> E 


^ 


ADX 


t t AUX 


E 21 » X j => E 21 




E 31 * X i => X J 


* 




E => W * N 

r 





13. c is 18-bit signed integer expansion of c. (0 < c < 37 ; -17 < c < + 17) 



3-7^ 



August 1963 



Ik. JMP, BRC variations: 



FUNCTION 


c 


ACTION 


d 
4.8 


t.7 


k.6 


4.5 


k.k 


JUMP 


- 


- 


- 


- 





r ==> P 


BRANCH 


- 


- 


- 


- 


1 


r © X, ==> P 


- 


- 


- 


- 





- 


.- 


SAVE 


- 


- 


- 


1 


- 


P ♦ 1 ==> Xj 


- 


- 


- 





- 


- 


- 


P + 1 => E 


- 


- 


1 


- 


- 


P + 1 ==> E 21 


- 


- 





- 


- 


- 


- 


Q ==> E 


- 


1 


- 


- 


- 


Q-=> \ 3 


- 





- 


- 


- 


- 


- 


DISMISS 


1 ' 


- 


- 


- 


- 


if h = 0, *=> <|> L 



15. TSD (Unit Ready) 



I normal i 

node 
{ out in j 



V => 



U K =>E 



E => U. 



J 



E => w A 



J 



assembly 

mode 

out in 



W rj => U K 




U K => W rj 


' 


1 




■ ■' 


" REV 




FWD " 


R " 1 W rj => W rj 







August 1963 



3-75 



CHAPTER 3 
INDEX 



NUMERICAL ORDER 



ALPHABETICAL ORDER 



CODE NO. 


OPERATION 


PAGE 


OPERATION 


CODE NO. 


PAGE 


4 


IOS 


4-7 


ADD 


67 


3-58 


5 


JMP 


3-30 


ADX 


15 


3-22 


6 


JPX 


3-26 


AUX 


10 


3-20 


7 


JNX 


3-26 


COM 


56 


3-50 


10 


AUX 


3-20 


CAB 


62 


3-42 


11 


RSX 


3-14 


CYA 


60 


3-42 


12 


SKX 


3-24 


CYB 


61 


3-42 


14 


EXX 


3-18 


DIV 


75 


3-62 


15 


ADX 


3-22 


DPX 


16 


3-16 


16 


DPX 


3-16 


DSA 


65 


3-46 


17 


SKM 


3-34 


EXA 


54 


3-10 


20 


LDE 


3-7 


EXX 


14 


3-18 


21 


SEF 


3-54 


FLF 


31 


3-55 


22 


SPG 


3-54 


FLG 


32 


3-55 


24 


LDA 


3-6 


INS 


55 


3-48 


25 


LDB 


3-6 


IOS 


4 


4-7 


26 


LDC 


3-6 


ITA 


41 


3-46 


27 


LDD 


3-6 


ITE 


40 


3-46 


30 


STE 


3-8 


JMP 


5 


3-30 


31 


ELF 


3-55 


JNA 


47 


3-32 


32 


FLG 


3-55 


JNX 


7 


3-26 


3^ 


STA 


3-8 


JOV 


45 


3-32 


35 


STB 


3-8 


JPA 


46 


3-32 


36 


STC 


3-8 


JPX 


6 


3-26 


37 


STD 


3-8 


LDA 


24 


3-6 


1*0 


ITE 


3-46 


LDB 


25 


3-6 


41 


ITA 


3-46 


LDC 


26 


3-6 


42 


UNA 


3-46 


LDD 


27 


3-6 


43 


SED 


3-36 


LDE 


20 


3-6 


45 


JOV 


3-32 


MUL 


76 


3-60 


46 


JPA 


3-32 


NAB 


66 


3-40 


47 


JNA 


3-32 


NOA 


64 


3-40 


54 


EXA 


3-10 


RSX 


11 


3-14 


55 


INS 


3-48 


SAB 


72 


3-38 


56 


COM 


3-50 


SCA 


70 


3-38 


57 


TSD 


4-9 


SCB 


71 


3-38 


60 


CYA 


3-42 


SED 


43 


3-36 


61 


era 


3-42 


SKM 


17 


3-34 


62 


CAB 


3-42 


SKX 


12 


3-24 


64 


NOA 


3-4o 


SPF 


21 


3-54 


65 


DSA 


3-46 


SPG 


22 


3-54 


66 


NAB 


3-40 


STA 


34 


3-8 


61 


ADD 


3-58 


STB 


35 


3-8 


70 


SCA 


3-38 


STC 


36 


3-8 


71 


SCB 


3-38 


STD 


37 


3-8 


72 


SAB 


3-38 


STE 


30 


3-8 


74 


TLY 


3-65 


SUB 


77 


3-58 


75 


DIV 


3-62 


TSD 


57 


4-9 


76 


MUL 


3-60 


TLY 


74 


3-65 


77 


SUB 


3-58 


UNA 


42 


3-46 



August 1963 



3-77